Xiangyu Tian
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ac3d53ff5d
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LLM: Fix vLLM CPU version error (#11206)
Fix vLLM CPU version error
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2024-06-04 19:10:23 +08:00 |
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Xiangyu Tian
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b3f6faa038
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LLM: Add CPU vLLM entrypoint (#11083)
Add CPU vLLM entrypoint and update CPU vLLM serving example.
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2024-05-24 09:16:59 +08:00 |
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Guancheng Fu
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990535b1cf
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Add tensor parallel for vLLM (#10879)
* initial
* test initial tp
* initial sup
* fix format
* fix
* fix
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2024-04-26 17:10:49 +08:00 |
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Guancheng Fu
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47bd5f504c
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[vLLM]Remove vllm-v1, refactor v2 (#10842)
* remove vllm-v1
* fix format
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2024-04-22 17:51:32 +08:00 |
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Xiangyu Tian
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08018a18df
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Remove not-imported MistralConfig (#10670)
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2024-04-07 10:32:05 +08:00 |
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Jiao Wang
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69bdbf5806
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Fix vllm print error message issue (#10664)
* update chatglm readme
* Add condition to invalidInputError
* update
* update
* style
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2024-04-05 15:08:13 -07:00 |
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Shaojun Liu
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a10f5a1b8d
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add python style check (#10620)
* add python style check
* fix style checks
* update runner
* add ipex-llm-finetune-qlora-cpu-k8s to manually_build workflow
* update tag to 2.1.0-SNAPSHOT
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2024-04-02 16:17:56 +08:00 |
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Wang, Jian4
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9df70d95eb
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Refactor bigdl.llm to ipex_llm (#24)
* Rename bigdl/llm to ipex_llm
* rm python/llm/src/bigdl
* from bigdl.llm to from ipex_llm
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2024-03-22 15:41:21 +08:00 |
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